----------------------------------------------------------------------------------
--32 bits shift operation
--operation index:
--00-> sll
--01-> sla (here we assume sla is to push in a '1' while shifting left)
--10-> srl
--11-> sra
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shifter_32bits is
    Port ( input : in  STD_LOGIC_VECTOR (31 downto 0);
           shift_value : in  STD_LOGIC_VECTOR (4 downto 0);
			  operation : in STD_LOGIC_VECTOR (1 downto 0);
           output : out  STD_LOGIC_VECTOR (31 downto 0));
end shifter_32bits;

architecture Behavioral of shifter_32bits is

	component shifter_Nbits is
	 generic (N : integer);
    Port ( input : in  STD_LOGIC_VECTOR (31 downto 0);
			  operation : in STD_LOGIC_VECTOR (1 downto 0);
           enable : in  STD_LOGIC;
           output : out  STD_LOGIC_VECTOR (31 downto 0));
	end component;


	signal after_1b : STD_LOGIC_VECTOR (31 downto 0);
	signal after_2b : STD_LOGIC_VECTOR (31 downto 0);
	signal after_4b : STD_LOGIC_VECTOR (31 downto 0);
	signal after_8b : STD_LOGIC_VECTOR (31 downto 0);
	
begin
	b1: shifter_Nbits generic map(1) port map (input, operation, shift_value(0), after_1b);
	b2: shifter_Nbits generic map(2) port map (after_1b, operation, shift_value(1), after_2b);
	b4: shifter_Nbits generic map(4) port map (after_2b, operation, shift_value(2), after_4b);
	b8: shifter_Nbits generic map(8) port map (after_4b, operation, shift_value(3), after_8b);
	b16: shifter_Nbits generic map(16) port map (after_8b, operation, shift_value(4), output);

end Behavioral;

